1. Field of the Invention
This invention is related to the field of integrated circuits and, more particularly, to power saving modes in integrated circuits and storage circuit operation during the power saving modes.
2. Description of the Related Art
The power consumption of integrated circuits (and methods for minimizing such power consumption, particularly when a given integrated circuit is not in use) are an important design consideration for modern integrated circuit designers. Many systems which employ the integrated circuits may operate on battery power at least some of the time (e.g. laptop computers, personal digital assistants, cellular phones, etc.). Since a finite amount of energy is available from the battery, reducing use of power by circuits that are not in use lengthens the amount of time that a given battery may continue to power the system. Additionally, even in systems in which power is plentiful (e.g. those connected to a wall socket), reducing power consumption may be beneficial. Most of the power consumed in systems is radiated as heat, which generally must be removed from the system. The thermal stress on the system may be reduced by reducing power consumption of the integrated circuits.
Dynamic power reduction mechanisms have included reduction of the clock frequency of an integrated circuit if the full performance of the integrated circuit is temporarily not needed, even to the point of stopping the clock signal (i.e. a clock frequency of zero). Storage circuits within the integrated circuit retain their values, but switching within the integrated circuit stops since the state of the integrated circuit is not changing. Accordingly, power dissipation due to the switching action is reduced.
An additional source of power consumption in integrated circuits is the leakage current that occurs in transistors whenever there is a voltage difference applied to the transistor terminals, even if the transistors are not actively conducting current. The clock stopping mechanism described above reduces the switching power consumption, but does not reduce the leakage current power consumption.
The frequency at which the transistors switch increases as the gate length of the transistor decreases. Accordingly, semiconductor fabrication processes continue to be improved to provide for shorter gate lengths. The leakage current also increases as the gate length of the transistors decreases, and thus the power consumption of an integrated circuit which is attributable to the leakage current increases as the gate length of the transistors within the integrated circuit decreases.
In order to reduce power consumption due to leakage current, some dynamic power reduction mechanisms may cause the state of the integrated circuit to be saved (e.g. by writing the state to memory) and then remove the power supply voltage from the integrated circuit. When operation of the integrated circuit is desired again, the integrated circuit may be powered up and the state restored. The time required to save and restore the state may limit the opportunity to remove power from the integrated circuit as a power saving measure. Instead, when power conservation for shorter periods of time is possible, clock stopping techniques may generally be used. Additionally, it may be complicated to collect all of the state from the integrated circuit for writing to memory.
A storage circuit for an integrated circuit is described which is configured to couple to a first power supply voltage (e.g. a Vdd power supply voltage used by other circuitry within the integrated circuit) in response to a deassertion of a hold signal and configured to couple to a second power supply in response to an assertion of the hold signal. The second power supply voltage may be the hold signal voltage or another power supply voltage separate from the Vdd power supply voltage. In use, the hold signal may be asserted and the Vdd power supply voltage may be removed. Leakage current in circuits powered only by the Vdd power supply voltage may be eliminated, while the storage circuit may retain its stored value. When the Vdd power supply is restored, the storage circuit may still be retaining its value and thus saving and restoring of the value in the storage circuit may not be required. A system including the integrated circuit and a method for managing power in a system including the integrated circuit are also described.
Broadly speaking, an apparatus is contemplated, comprising at least one memory cell having a power input and a circuit coupled to the power input. The circuit is coupled to receive a first power supply voltage and further coupled to receive a first signal. The circuit is configured to supply the first power supply voltage to the power input in response to the first signal being deasserted, and is configured to supply a second power supply voltage to the power input in response to the first signal being asserted.
Additionally, an integrated circuit is contemplated, comprising a plurality of storage circuits. Each storage circuit is coupled to receive a first signal, and is configured to couple to a first power supply voltage for power in response to the first signal being deasserted. Each storage circuit is further configured to couple to a second power supply voltage for power in response to the first signal being asserted.
Moreover, a system is contemplated. The system comprises an integrated circuit including a plurality of storage circuits and logic circuitry. Each storage circuit is coupled to receive a first signal, and is configured to couple to a first power supply voltage for power in response to the first signal being deasserted. Additionally, each storage circuit is configured to couple to a second power supply voltage for power in response to the first signal being asserted. The logic circuitry is coupled to the plurality of storage circuits and to receive the first power supply voltage. The system also comprises a control circuit configured to assert the first signal and to cause a removal of the first power supply voltage.
Still further, a method is contemplated. A first signal is asserted to a plurality of storage circuits. Each storage circuit is configured to couple to a first power supply voltage for power in response to the first signal being deasserted, and each storage circuit is configured to couple to a second power supply voltage for power in response to the first signal being asserted. The first power supply voltage is removed.